`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:58:10 05/23/2012
// Design Name:   HardwareTestbench_SpiNorFlashController
// Module Name:   /home/azonenberg/native/programming/achd-soc/trunk/hdl/achd-soc/testHardwareTestbench_SpiNorFlashController.v
// Project Name:  achd-soc
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: HardwareTestbench_SpiNorFlashController
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module testHardwareTestbench_SpiNorFlashController;

	// Inputs
	reg clk_20mhz = 0;
	reg uart_rx = 1;

	// Outputs
	wire spi_sck;
	wire spi_cs_n;
	wire [7:0] leds;
	wire uart_tx;

	// Bidirs
	wire [3:0] spi_data;

	// Instantiate the Unit Under Test (UUT)
	HardwareTestbench_SpiNorFlashController uut (
		.clk_20mhz(clk_20mhz), 
		.spi_sck(spi_sck), 
		.spi_cs_n(spi_cs_n), 
		.spi_data(spi_data), 
		.leds(leds),
		.uart_rx(uart_rx),
		.uart_tx(uart_tx)
	);
	
	//The SPI flash
	s25fl008k #(
		.UserPreload(1),
		.mem_file_name("/home/azonenberg/native/programming/achd-soc/trunk/testprogs/13_mm/mm.hex"),
		.screg_file_name("none"),
		.unique_id(64'hdeadbeefbaadc0de)
	) flash (
		.SI(spi_data[0]), 
		.SO(spi_data[1]),
		.SCK(spi_sck),
		.CSNeg(spi_cs_n), 
		.HOLDNeg(spi_data[2]), 
		.WPNeg(spi_data[3])
		);

	reg ready = 0;
	initial begin
		#100;
		ready = 1;
	end
	
	always begin
		#25;
		clk_20mhz = 0;
		#25;
		clk_20mhz = ready;
	end
      
endmodule

